期末考

module top;
wire A, B, C, D;
system_clk #50 clk1(D);
system_clk #100 clk2(C);
system_clk #200 clk3(B);
system_clk #400 clk4(A);
comparator c1 (A, B, C, D, F);
endmodule


module comparator(A, B, C, D, F);
input A, B, C, D;
output F;
wire f1,f2,f3,f4,c1,c2,c3,c4;
not (c1 ,A);
not (c2 ,B);
not (c3 ,C);
not (c4 ,D);

and (f1 ,c1 ,c2 ,c3);
and (f2 ,D ,c1);
and (f3 ,c3 ,A ,D);
and (f4 ,A ,c4 ,C);

or (F, f1, f2, f3, f4);
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

9

module top;
wire o,a1;

system_clk #100 clk2(a1);
nanf201 c1 (o,a1);
endmodule



module nanf201(o,a1);
input a1;
output o;
nand (o,a1);
specify
specparam
Tpd_0_1=1.13:3.09:7.75,
Tpd_1_0=0.93:2.5:7.34;
(a1=>o)=(Tpd_0_1,Tpd_1_0);

endspecify
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(49*period/50)clk=~clk;
#(period-49*period/50)clk=~clk;
end
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

8

module top;
wire [3:0] x_in;
wire y_out;
system_clk #50 clk1(x_in[0]);
system_clk #100 clk2(x_in[1]);
system_clk #200 clk3(x_in[2]);
system_clk #400 clk4(x_in[3]);
and4_algo c1 (y_out, x_in);
endmodule


module and4_algo(y_out,x_in);
input [3:0] x_in;
output y_out;
reg y_out;
integer k;
always@(x_in)
begin : and_loop
y_out=1;
for(k=0;k<=3;k=k+1)
if(x_in[k]==0)
begin
y_out=0;
disable and_loop;
end
end
endmodule


module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

7-1

module top;
wire [3:0] x_in;
wire y_out;
system_clk #50 clk1(x_in[0]);
system_clk #100 clk2(x_in[1]);
system_clk #200 clk3(x_in[2]);
system_clk #400 clk4(x_in[3]);
and4_rtl c1 (y_out, x_in);
endmodule


module and4_rtl(y_out, x_in);
input [0:3] x_in;
output y_out;
assign y_out = &x_in;
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

7

module top;
wire x_in1 ,x_in2 ,x_in3 ,x_in4;
system_clk #50 clk1(x_in4);
system_clk #100 clk2(x_in3);
system_clk #200 clk3(x_in2);
system_clk #400 clk4(x_in1);
and4_rtl cl (y_out ,x_in1 ,x_in2 ,x_in3 ,x_in4);
endmodule


module and4_rtl(y_out ,x_in1 ,x_in2 ,x_in3 ,x_in4 );
input x_in1 , x_in2 , x_in3 , x_in4;
output y_out;
assign y_out = x_in1 & x_in2 & x_in3 & x_in4;
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

text6

text5

test3

test2

test1